This invention relates generally to timing recovery of higher order modulated radio frequency communications, and, more specifically, to such radio frequency communications systems wherein the digital-to-analog and analog-to-digital conversion oversampling frequencies required to properly synchronize phase becomes excessively expensive due to the bandwidth requirements associated with a radio frequency waveform or lack of frequency tunability. This invention also relates to the field of digital interpolation of non-coherent sampled signals.
The Digital-to-analog convertor (DAC) samples at a specific, typically rising, edge of a clock that is as close in phase to the modulation clock as possible. To assist in determining the phase of the clock without a known sequence (non-data aided) transmitted, communications systems typically oversample the signal and perform analog recovery loops or digital timing recovery schemes. The majority of digital timing recovery schemes require a minimum oversampling of twice (though some require 4×) the symbol rate. Furthermore, these techniques further restrict oversampling to an integer multiple. Many system requirements (desired throughput, bit error rate, bandwidth) drive derived requirements that may preclude component selection (analog filters due to pass bands, digital boards with inadequate clock frequencies, etc.). Ultimately, the choice of available hardware may prevent the transmitter-receiver pair from operating with an integer multiple sampling factor. Decimal oversampling at the transmitter would render many digital timing recovery techniques useless. In addition, many timing recovery schemes are not suited for higher order modulations, i.e. 16-Quadrature Amplitude Modulation (16-QAM), as they rely on zero crossings for phase error calculations and sampling adjustments.
An optimal solution to the timing recovery of received signals is a reconfigurable, all digital scheme capable of analyzing and adjusting incoming symbols oversampled at any decimal value at or above 2×. Feedback can be given to the Analog-to-Digital convertor's clock via a numerical controlled oscillator, but results shown for 16-QAM recovery compensate on a free-running clock without feedback. The prior art has been able to isolate each of these parameters independently, but has failed to optimize for all parameters at once without expansive processing. Specifically, the prior art still either uses analog recovery loops prone to component tolerances or complex (memory and processing intensive) interpolation and decimation schemes.
In “A BPSK/QPSK Timing-Error Detector for Sampled Receivers,” a digital timing recovery scheme is proposed that has served as the basis for many digital synchronization techniques. This requires integer multiple oversampling of a Binary Phase Shift Keying or Quadrature Phase Shift Keying modulation; both of which do not apply to the problem this invention intends to solve.
In U.S. Pat. No. 5,495,203, a QAM demodulator with non-integer sampling is used to interpolate, and then decimate an incoming signal. The resampled signal is feed into a control loop to recover the data rate and continuously tunes interpolation and decimation until locked to the intended data. A limitation to this approach, potentially, is the complexity of the interpolation and decimation values to approximate oversampling rates needed.
In U.S. Pat. No. 5,878,088, a variable symbol timing recovery scheme is proposed with two stage interpolation and decimation controlled by multiplexors and based on the phase error within the control loop. This allows the system to increase or decrease the level of granularity needed to estimate the QAM symbol data and adjust a numerically controlled oscillator as needed. However, this invention may be affected by excessive delay and control overhead to synchronize the varying interpolation and decimation stages.
In U.S. Pat. No. 6,295,325, an arbitrary oversampling timing recovery loop is proposed. The invention is capable of taking any symbol data rate and oversample by an integer multiple. The flexibility of the oversampling is convenient, but a situation where the oversampling frequency is not an integer multiple of the symbol data rate is an issue.
In U.S. Pat. No. 6,854,002, an analog high speed interpolation apparatus is proposed, allowing for low latency corrections of the oversampling of a received signal within a timing recovery loop. While a promising invention, the necessity for complex and expensive analog components is a limiting factor.
In U.S. Pat. No. 7,149,265, a timing recovery loop is proposed with reconfigurable non-integer oversampling. A configurable number of parallel elements examine whether a delay is occurring from the previous sample (within the same element) and if a shift is found within that sampling cycle (element-to-element) and adjust a counter to numerically control incoming samples. This invention requires the sample rate to be a rational number p/q where the number of parallel elements, N, is an integer factor of q. This restricts the selection of p and q; thus the selection of the sampling frequency, which may be limited to the system hardware.